The present invention relates to a memory cell and a memory comprising such a memory cell.
Volatile memories as SRAM, DRAM and embedded DRAM are essential building blocks of modern IC designs. They offer exceptional speed and endurance, but they are volatile memories and therefore rely on an external power supply to keep their memory state. If the power source is switched off, the memory state is lost.
Nonvolatile memories, such as flash memories, have reached maturity, but suffer from exceptionally low speed and endurance. Emerging nonvolatile memory concepts such as FeRAM, STT-MRAM, ReRAM, PC-RAM, etc. are very fast and are in principle capable of replacing DRMA and SRAM, but despite the fact that they have been researched for more than a decade, their limited endurance, scalability and manufacturability have prevented a breakthrough.
In order to combine high memory speed and easy manufacturability of, for example, SRAM technology with non-volatility, it is possible to add additional nonvolatile components to conventional volatile memories, such as an SRAM, in order to prevent data loss for example at scheduled power off or even unscheduled, for example, emergency off. This can be obtained, for example, by adding an additional nonvolatile memory, i.e. an NVM element to a volatile memory, i.e. a NV-SRAM is generated, a combination of a conventional SRAM and a SONOS cell.
FIG. 18 shows an example of a nonvolatile memory structure according to the just sketched option. The combination of an NVM memory with a fast and enduring volatile memory is converted, according to FIG. 18, to an NV-SRAM, a combination of a conventional 6T-SRAM cell with a flash memory cell as distributed, for example, by ANVO Systems. However, due to the incorporation of an additional NVM element, the memory density deteriorates enormously. Additional circuitry and power supply control with emergency high energy storage capacitors exemplarily exists as a further component of the NV-SRAM concept in the case of FIG. 18 in order to restore the SRAM cell into the allocated flash memory cell in case of an emergency.
The solution presented in FIG. 18, however, necessitates additional chip area and integration effort in the form of, for example, additional process steps or an additional lithography step.